Semiconductor circuits integrated into a semiconductor chip contain what are known as ESD protective circuits to protect the inputs or outputs (I/O ports) against electrostatic overvoltages and electrostatic discharge (ESD=electrostatic discharge) caused as a result. ESD protective elements can be formed, for example, as thyristors, bipolar transistors, diodes or a mixture thereof. ESD protective elements are known generally in a large number of embodiments, so that their construction and function will not be discussed in more detail below.
These ESD protective circuits are typically connected between an input path of an integrated circuit and the input or output terminal to be protected and ensure that, if a parasitic overvoltage pulse is injected which, in the extreme case, could lead to the destruction of the integrated circuit, the ESD protective element turns on and the parasitic overvoltage pulse is thus conducted away.
It is important in this case to know the ESD interference pulse expected as accurately as possible, in order therefore to adapt the design and the dimensioning of the corresponding ESD protective structure as well as possible thereto. For the simulation of an interference signal injection, use is very frequently made of what is known as the human body model (HBM), which simulates parasitic peak currents of a few amperes lasting about 100 ns. The equivalent circuit of the HBM model provides for a low-pass filter consisting of a capacitance of about 100 pF and a resistance of about 1.5 kΩ. The HBM model is usually used when the interference pulse expected is caused by a human. Alternatively, it would also be conceivable for the ESD pulse to be caused by metallic objects. In this case, what is known as the machine model (MM) is used. Furthermore, there also exist other models, such as what is known as the charged device model (CDM), in which it is assumed that the integrated circuit is itself charged out and an interference pulse arises as a result of a discharge to earth. These models are used to simulate a parasitic interference pulse to be expected and are used to design the corresponding ESD protective structures to match the interference pulse to be expected.
With the continuing increasing complexity involved in electronic systems and integrated circuits, for example applicator-specific integrated circuits (ASICs) or “systems on chips” (SOCs), greater and greater significance is assigned to the test and the verification of just to these circuits and systems. During this verification, the relevant system characteristics are qualified and quantified.
Furthermore, the importance of the ESD protection in integrated circuits rises with the requirements on operating speed, which is higher and higher, a lower operating voltage, a higher packing density of the individual components and the special requirement of providing more and more beneficial circuits. This generally leads to thinner and thinner dielectric layers, higher doping concentrations with abrupt doping transitions and higher electric fields occurring. Each of these factors leads to an increased sensitivity of the ESD effects.
Added to this is the fact that the system characteristics of highly complex integrated circuits are increasingly determined by the interaction of the integrated hardware with the application software which, for example, is provided by a device manufacturer, so that in modern systems the hardware can no longer be evaluated separately from the application software. Since, typically, the major part of the hardware-based system characteristics are already defined at a very early development phase, it is critical that, in interaction with the application software, the respectively optimal architecture which, in particular, is optimized with regard to ESD protection, is determined.
Despite optimal design of the ESD protective structures on the integrated circuit to be protected, in general the removal of the ESD sensitivity can never be wholly eliminated. The cause of this lies in the increasing complexity of the integrated circuits, in which, even adjacent circuit blocks can have a mutually positive or else negative influence. This influencing of adjacent circuit parts becomes all the more serious the smaller the respective circuit parts are formed and the more densely the adjacent circuit parts are arranged in relation to one another. This mutual influencing of individual circuit parts of the integrated circuit is caused by the specific design of this integrated circuit. Information as to how a specific design of an integrated circuit will affect the ESD protection can currently be obtained only after the design phase, for example by using a prototype of the integrated circuit. As a result, in the extreme case, this can lead to a redesign of the circuit. However, the problem with this is that the development cycles for highly integrated circuits in modern CMOS, BICMOS or bipolar technologies are becoming shorter and shorter. In addition to the loss in time for a requisite redesign, this measure is also costly, since here the different mask sets very frequently have to be adapted to the new design.
At present, ESD protection is in each case provided for individual components or circuit parts of an integrated circuit. Here, by means of suitable adaptation of the design rules and dimensions, optimal protection for just these components can be obtained. However, it is a problem that, here, a mutual influence of adjacent circuit blocks is not taken into account. Adjacent circuit blocks can have a positive or else negative influence with regard to the ESD pulses injected. In the case of a positive influence, this means that, for example, the ESD protection for a circuit part is normally over-dimensioned or is even unnecessary. In the case of a negative influence, however, it is possible for the ESD protection for a circuit part, which is typically adequate for this circuit part, now to be inadequate because of the negative influence of adjacent circuit parts, which, in the extreme case, could lead to the integrated circuit being damaged or destroyed in the event that a parasitic overvoltage pulse is injected.
For some time, therefore, great efforts have been made also to permit the design for the assessment of the ESD resistance of an integrated circuit with the complexity of a typical digital or mixed-signal IC. In this case, as early as in the design phase, an integrated circuit is examined for its ESD functionality and therefore for its ESD protective action by means of a virtual ESD test.
The particular difficulty resides here in particular in the complexity of the physical mechanisms and the necessity of simulating all of the integrated circuit, since only in this way can critical ESD current paths be found. The problem with this is that the methods available nowadays entail such a great deal of effort on configuration and extraction that a simulation of the ESD protection of an entire semiconductor chip could barely be used productively for the verification of the integrated circuit in the pre-chip phase. A commercial solution to this simulation task is currently not available.
FIG. 1 shows the structure of a known ESD simulation system for the ESD verification of an integrated circuit, as disclosed by U.S. Pat. No. 6,493,850 B2. In this case, FIG. 1 results from combining FIGS. 1 and 2 of U.S. Pat. No. 6,493,850 B2.
The ESD simulation system 100 described there has a pre-processor 100 which, on the output side, generates simulation data 120 which are supplied to the simulator 130. Connected downstream of the simulator 130 is a post-processor 140 and an output data generator 150 connected downstream of the latter. The core of the ESD simulation system in U.S. Pat. No. 6,493,850 B2 is the pre-processor 110, which is used to obtain the simulation data. The pre-processor 110 has four information generators 210, 220, 230, 240. The first information generator 210 produces a network list from the layout data 212 (layout file) and the data for the individual wiring patterns of the various components 213 (schematic file). The second information generator 220 generates a component model 221. The third information generator 230 generates data 231 for what is known as a safe operating state (safe operating file) for the entire integrated circuit. In the fourth information generator 240, the simulation conditions 241 are provided. The data 211, 221, 231, 241 are injected together into a translator 250, which generates the simulation input data 120 for the simulator 130 therefrom.
For the quantitative identification of the ESD sensitivities and latch-up effects in a design of an integrated circuit, even before the production of the integrated circuit, the data 211, 221, 231, 241 are combined and a simulated, quantified ESD event is applied to the design of the integrated circuit. The ESD sensitivities resulting from this on the design elements are observed and analysed quantitatively. Critical stress values in the design are assessed and failures of ESD protective elements are recorded. After running through the entire simulation, finally a list of those ESD protective elements and locations which function correctly and those which have failed is output. This information can be used for optimizing the design with regard to improved ESD protection.
In order to assess the ESD resistance of a design, however, in U.S. Pat. No. 6,493,850 a great deal of effort on extraction and modelling is required on the basis of the requirement for a very high and accurate simulation of the physical model of the integrated circuit. The high effort on extraction results in particular from the fact that, here, the simulation is carried out at the layout level of the integrated circuit. For the simulation, exorbitantly high computing power, and therefore a very long computation time, are therefore necessary, which lengthens the pre-development phase of the integrated circuit overall.
The simulation of the ESD sensitivities is, moreover, highly dependent on the accurate knowledge of a physical model of the integrated circuit. However, this is not always available, so that the reliability of the simulation here is not particularly high.
A further disadvantage is that variations in the technological parameters and the design environment are not taken into account here during the simulation of the ESD sensitivity.
In U.S. Pat. No. 6,493,850 B2, the ESD verification is performed only on a complete layout of the integrated circuit. Verification before the layout phase, for example during or immediately after the design phase or product definition phase, is not possible here, so that the ESD test data are available only relatively late, which means that the development time of the integrated circuit lasts for a relatively long time.